1. Field of the Invention
The present disclosure relates to state machines and in particular those used in integrated circuits.
2. Description of the Related Art
A state machine is a sort of automaton the operation of which is modeled by a set of states linked to each other by transitions. A finite state machine comprises a finite number of states, each state being determined by the so-called state values of a set of signals. The change from a current state to a next state linked to the current state by a transition is performed according to the state signals.
Classically, a state machine comprises input signals and output signals generated according to the input signals upon each transition triggered by an active edge of a clock signal. The input and output signals of a state machine may include primary signals and secondary signals. The primary input signals are the signals that the state machine receives from the “external environment”. The primary output signals are the signals that the state machine sends to the external environment. The secondary output signals produced by the state machine are stored, for example, using flip-flops to be used as secondary input signals upon the next transition.
FIG. 1 represents a state machine in block form. In FIG. 1, the state machine FSM 100 comprises a combinational logic circuit CBL 102 and a set of latches LTS 104. All the secondary outputs 106 of the circuit CBL 102 are connected to the set of latches LTS 104. The circuit CBL 102 comprises primary inputs PI 108 and primary outputs PO 110. The circuit CBL 102 also comprises secondary inputs SI 112 and secondary outputs SO 106. The secondary outputs SO 106 are connected to the set of latches LTS 104. Sometimes, some or all of the primary outputs 110 may also be secondary outputs 106. The latches of the set LTS 104 enable the current state of the state machine to be stored, i.e., the last values of the primary and secondary output signals generated by the state machine may be stored in the latches of the set of latches LTS 104. The secondary output signals, once locked by the set of latches LTS, become the secondary input signals SI used by the circuit CBL to execute the next transition.
Many electronic circuits use state machines. This is particularly the case of certain memories such as serial access EEPROM (Electrically Erasable Programmable Read-Only Memory) memories.
In such applications, the transitions are generally performed in synchronization with a clock signal CLK 114 supplied by a communication bus. The primary input signals generally comprise signals received by the memory, and other signals internal to the memory. The primary output signals are control signals controlling various subsets of the memory (shift registers, memory array decoders, read circuitry, charge pump, etc.).
Certain state machines of integrated circuits are produced using programmable logic arrays PLA. A logic array may comprise an AND array and an OR array each comprising so-called dynamic logic gates. The operation of such logic gates is paced by the clock signal that defines phases of precharging and evaluating the state of the logic gates. The clock signal applied to the state machine corresponds to the external clock signal applied to the integrated circuit when the latter is selected.
The precharge phase may be performed, for example, when the clock signal is in the low state. Upon the rising edge of the clock signal that triggers the evaluation phase, the input signals of the logic array are sampled. During the evaluation phase, the AND and OR arrays are decoded to obtain the output signals of the state machine.
Generally, for the state machine to operate correctly, the input signals should not change state just before and during the active edge of the clock signal CLK. Indeed, an excessively high clock frequency (excessively short evaluation phase in the case of a logic array) generally causes the production of incorrect output signals, which causes the state machine or the assembly (integrated circuit) into which the state machine is integrated to malfunction or even crash. In the case of a memory, such a malfunction can result, for example, in the decoding of incorrect commands, in read (thus reversible) or write (irreversible) data corruption, or in the memory crashing, which can require an initialization by switch-off followed by switch-on.
A disturbance of the clock signal may cause a state machine to malfunction. A disturbance of the clock signal can be involuntary (for example noise on the clock signal of an access bus, interpreted as a brief clock knock), or voluntary. In the latter case, it may be attempts to disturb the operation of a secure circuit, so as to try to violate a securitization function. Indeed, certain EEPROM memories, such as those adapted to specific applications, have securitization functions the operation of which may be more or less linked to the state machine.